A programmable logic device where a circuit configuration is changed by a program includes a semiconductor integrated circuit, for example, a Field Programmable Gate Array (FPGA). The FPGA may include a variable-logic logic block including a look-up table memory, and a switch matrix programmably wire-connecting the variable-logic logic block. The address line of the look-up table corresponds to a logical input, and the output thereof corresponds to a logical operation result. The data of the look-up table is rewritten, and hence a logic block equivalent to an arbitrary logical operation is generated. The output of the logic block is wired through a connection box so as to be wire-connected to another logic block by a switch box programmably switched. For example, in the FPGA, the logic block, the switch box, and the connection box may be disposed in a checkered pattern-like array form. Configuration (reconfiguration) is performed where the data of the look-up table, the data of the switch box, or the data of the connection box is preliminarily set.
In the FPGA of an application, after power activation, configuration information is transferred to the inside of a device, and a clock is applied (batch reconfiguration). In a partial reconfiguration-type FPGA, the configuration of a portion of a circuit block is changed during operation. A circuit used for isolating the logic block and the switch matrix from another logic block group in terms of a circuit is added, and the configuration information of the logic block is rewritten during the operation of another circuit.
A related technique has been disclosed in U.S. Pat. No. 6,526,557 or the like.